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Doubling the integer resources but not the FP resources works even better when you look at AMD’s whole motivation behind Fusion. Much heavy FP work is expected to be moved to the GPU anyway, there’s little sense in duplicating FP hardware on the Bulldozer core when it will eventually have a fully capable GPU sitting on the same piece of silicon. While the first incarnation of Bulldozer, the Zambezi CPU, won't have an on-die GPU, presumably future APUs will use the new core. In those designs the Bulldozer cores and the GPU will most likely even share the L3 cache. It’s really a very elegant design and the basis for what AMD, Intel and NVIDIA have been talking about for years now. The CPU will do what it does best while the GPU does what it is good at.
Zanimljivo .... da li će se ovaj Buldozer blok voditi kao 1 ili 2 jezgra?
To je jasno ... nego u smislu AMDovih roadmap grafikona.
Tamo pričaju o "ap to 8-core" procesorima, e sad da li to znači 4 Buldozer bloka ili 8 (16 logičkih procesora). Granica između logičkog i fizičkog procesora je sada prilično zamuljana, može proći pod oboje.
AMD notes that this core is a synthesizable IP block that's designed to be mixed and matched with other blocks on an SoC. What this means in English is AMD stores the CPU block in a high-level description language that then gets compiled down into logic gates and laid out on the chip by an automated toolset. The decision to do things this way, vs. the traditional method of customizing a lot of the lower-level design by hand, means trading off performance and some power efficiency for flexibility and time-to-market.
http://www.maximumpc.com/article/news/amd_banks_accelerated_processing_unitsWith synthesizable CPUs, engineers use software to design the circuits instead of creating each by hand. Similar to programming in C++ rather than machine code, AMD said there is roughly a 20 percent clock penalty by making Bobcat synthesizable but the power savings and the flexibility of it make it a “no brainer.”
AMD will commit to bringing out one new major revision of an APU per year, Akrout said. But AMD's roadmaps show two APUs that will be launched in 2011: "Llano," an APU for desktop-replacement notebooks and mainstream desktops; and "Ontario," an APU for the ultrathin notebook and possibly the netbook market. Rick Bergman, the senior vice president overseeing AMD's product group, said that Llano and the server version of "Bulldozer" would both be manufactured on a 32-nm SOI technology.
Traditionally, CPUs have been optimized for programmability, and GPUs have been designed for maximum throughput. Now, with Fusion, the GPU is being optimized for programmability, while the CPU is being tuned to improve throughput, executives said.
u slici:Da, samo što to nisu klasična jezgra. Jedan Bulldozer block može funkcionirati kao 2 fizička jezgra (sa dijeljenom FP jedinicom), ili kao jedno, ovisno o potrebi.
8 "jezgara" (4 bloka) bi bilo nešto kao ekvivalent današnjem quad core procesoru ... ipak je nekako logičnije gledati blok kao klasično jezgro s obzirom da je to nedjeljiva cjelina. 16-core (8 blokova) nije toliko nemoguće na 32nm, ako je 6-core moguće sada na 45nm.
Pa ne zna se,samo se kaze "negde u 2011 godini", koliko sam ja načuo, verovatno ili u aprilu 2011. ili u septembru 2011.
Kreni ti da odvajaš pare,biće skupo,samo da te upozorim,D-Devil.
One thing that has been confirmed is that the Bulldozer core has been shown to be incredibly resilient during early manufacturing samples, so much so that AMD has told us that it is experimenting using the 28nm bulk silicon process with only small changes to the die. Although AMD has not confirmed that they will use half stepping, they didn’t deny it either.
One of the first things that AMD confirmed for us was that the upcoming AM3+ will be the last of the pin grid array (PGA) and that all upcoming processor would be land grid array (LGA) more on that later.
The current AM3 Phenom II only use 938 pins, the upcoming Bulldozer and Bobcat cores will use all 941 pins. One of the benifiets of the AM3+ is that all AMD chips will be able to use DDR3 1866 (PC3 -15000) for staggering 60000MB/s as well as having advanced powersavings.
Going forward AMD’s will implement AMD’s Future socket or AMD’s Fusion socket, (Socket AF1) a massive Socket 1591 pins sock that will be the first of AMD’s next generation sock supporting DisplayPort 1.2, Full PCI Express 3.0 32 lane, and the addition of two more DDR channels allowing for quad channel memory.
a i zasto bi?Mislim da se triple channel nikad nije pominjao u kontekstu AMDa
Ali ima i kontradiktornosti jer sam negde pročitao da bi Buldožer procesori trebali da budu prvi AMD-ovi desktop use procesori u LGA izvedbi. Samim tim je nemoguće da budu kompatibilni sa AM3 pločama...
a i zasto bi?
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