Additive latency also known as CAS latency is another modification introduced into the DDR2 standard. It is designed to minimise instruction scheduler idles during data transmission to/from the memory. To illustrate this, let's take data read from a DDR2 device in the following conditions: Bank Interleave, additive latency = 0 (which is equal to read from a standard DDR memory).
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The first stage features the bank opening with the help of the ACTIVATE instruction and the provision of the first component of the address (line address), which selects and activates the necessary bank and the line in its array. During the next stage, the information is transmitted to the internal data bus and then goes to the sense amplifier. When an amplified noise level reaches the necessary value (after the latency time between line address and column identification, tRCD (RAS-to-CAS Delay) has elapsed), a READ with Auto-Precharge (RD_AP) instruction can be sent for execution along with the address column, in order to select a precise address of the data that are to be read from the sense amplifier. After the read instruction comes the execution of CAS latency (tCL), during which the data selected from the sense amplifier are syncronised and transmitted to the chip's external pins. It can create a situation where the next instruction (ACTIVATE) can't be sent for execution as other instructions hasn't yet been executed. Thus, if we take our example, the activation of the second bank has to be put off by one clock, as the execution of RD_AP from bank 0 is still in process. In the end, it leads to a break in the succession of data arrival via the external bus, which reduces real memory bandwidth.
To eliminate it and increase the efficiency of the instruction scheduler, the notion of additive latency (tAL) is introduced into DDR2. When tAL is not equal to zero, the memory device monitors READ (RD_AP) and WRITE (WR_AP) instructions, but postpones their execution by the time equal to the additive latency value. The picture below shows the difference in DDR2 chip's behaviour caused by two different tAL values.
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The picture above describes DDR2 chip functioning at tAL = 0, which is equivalent to a standard DDR device; the one below illustrates the case when tAL = tRCD - 1, which is typical of DDR2. Given this configuration, ACTIVATE and READ instructions can arrive for execution one by one. The actual realisation of the READ instruction will be postponed by the additive latency value, that is, it will be executed at the same moment as shown in the diagram above.
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This picture illustrates data read from DDR2 chip if tRCD = 4 clocks, which makes tAL = 3 clocks. In this case, due to the additive latency, ACTIVATE/RD_AP instructions will be executed in a row, enabling a continuous data arrival and a maximised real memory bandwidth.
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