- Učlanjen(a)
- 21.07.2003
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Ji 4Tze je napisao(la):
Hvala komsija, now back to the drawing board...
EDIT:
Mislim da bi ovo trebalo da radi sada. Probaj ponovo ako te ne mrzi.
Poslednja izmena:
Molba za test programa
- Začetnik teme audiofreak
- Datum pokretanja
Hvala komsija, now back to the drawing board...
EDIT:
Mislim da bi ovo trebalo da radi sada. Probaj ponovo ako te ne mrzi.
- Učlanjen(a)
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Ji 4Tze je napisao(la):nesto i ne radi ?
Kako ne radi? Pa vidis da sad pise Dual-Core : yes, a HyperThreading : no?
One nule pri dnu zanemari, trebalo bi da se ne ispisuje taj tekst kad nema vrednosti ali me mrzelo da stavljam if. :d
Inace to je deterministic cache parameter leaf koji daje detaljnije informacije o cache hijerarhiji i koji intelovi procesori podrzavaju a AMD-ovi ne. Zato su kod tebe nule.
Poslednja izmena:
Barton Socket A, NForce2:
CPU Brand String : AMD Athlon(tm) XP 3200+
CPU frequency : ~2200 MHz
CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : yes
3DNow! Instructions : yes
3DNow!+ Instructions : yes
SSE Instructions : yes
SSE2 Instructions : no
SSE3 Instructions : no
Denormals Are Zeros : no
Hyper-Threading : no
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : no
No Execute : no
LAHF/SAHF in x86-64 : no
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no
CPU cache & TLB info
--------------------
L1 ITLB 4K page : 16 entries, fully associative
L1 ITLB 2M page : 8 entries, fully associative
L1 ITLB 4M page : 4 entries, fully associative
L1 DTLB 4K page : 32 entries, fully associative
L1 DTLB 2M page : 8 entries, 4-way set associative
L1 DTLB 4M page : 4 entries, 4-way set associative
L2 DTLB 4K page : 256 entries, 4-way set associative
L2 ITLB 4K page : 256 entries, 4-way set associative
L1 instr. cache : 64KB, 2-way set associative, 64 byte line size
L1 data cache : 64KB, 2-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 512KB, 16-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
Addressing capability
---------------------
Physical address bits : 34
Virtual address bits : 32
Example
-------
Optimal block size : 16KB
Will use SSE code
CPU Brand String : AMD Athlon(tm) XP 3200+
CPU frequency : ~2200 MHz
CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : yes
3DNow! Instructions : yes
3DNow!+ Instructions : yes
SSE Instructions : yes
SSE2 Instructions : no
SSE3 Instructions : no
Denormals Are Zeros : no
Hyper-Threading : no
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : no
No Execute : no
LAHF/SAHF in x86-64 : no
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no
CPU cache & TLB info
--------------------
L1 ITLB 4K page : 16 entries, fully associative
L1 ITLB 2M page : 8 entries, fully associative
L1 ITLB 4M page : 4 entries, fully associative
L1 DTLB 4K page : 32 entries, fully associative
L1 DTLB 2M page : 8 entries, 4-way set associative
L1 DTLB 4M page : 4 entries, 4-way set associative
L2 DTLB 4K page : 256 entries, 4-way set associative
L2 ITLB 4K page : 256 entries, 4-way set associative
L1 instr. cache : 64KB, 2-way set associative, 64 byte line size
L1 data cache : 64KB, 2-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 512KB, 16-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
Addressing capability
---------------------
Physical address bits : 34
Virtual address bits : 32
Example
-------
Optimal block size : 16KB
Will use SSE code
- Učlanjen(a)
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E dobro, detekcija features i cachea radi kako treba ocigledno, dual-core .vs. htt je sredjeno (valjda) -- jos uvek niko sa Pentium EE 955? Treba mi to da bi znao da li detektuje HTT i dual-core kad ima oba, a ne samo odvojeno.
Poslednja izmena:
drfedja
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audiofreak je napisao(la):
Kod:
CPU Brand String : Dual Core AMD Opteron(tm) Processor 165
CPU frequency : ~2700 MHz
CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : yes
3DNow! Instructions : yes
3DNow!+ Instructions : yes
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : yes
Denormals Are Zeros : yes
Hyper-Threading : yes
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : yes
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no
CPU cache & TLB info
--------------------
L1 ITLB 4K page : 32 entries, fully associative
L1 ITLB 2M page : 8 entries, fully associative
L1 ITLB 4M page : 4 entries, fully associative
L1 DTLB 4K page : 32 entries, fully associative
L1 DTLB 2M page : 8 entries, fully associative
L1 DTLB 4M page : 4 entries, fully associative
L2 DTLB 4K page : 512 entries, 4-way set associative
L2 ITLB 4K page : 512 entries, 4-way set associative
L1 instr. cache : 64KB, 2-way set associative, 64 byte line size
L1 data cache : 64KB, 2-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 1024KB, 16-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
Addressing capability
---------------------
Physical address bits : 40
Virtual address bits : 48
Example
-------
Optimal block size : 32KB
Will use Hyper-Threaded code
Will flush Denormals to Zero
Will use SSE3 code
Poslednja izmena:
Tiger
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C:\123>pinfo
CPU Brand String : AMD Athlon(tm) 64 Processor 2800+
CPU frequency : ~1980 MHz
CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : yes
3DNow! Instructions : yes
3DNow!+ Instructions : yes
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : no
Denormals Are Zeros : yes
Hyper-Threading : no
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : no
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no
CPU cache & TLB info
--------------------
L1 ITLB 4K page : 32 entries, fully associative
L1 ITLB 2M page : 8 entries, fully associative
L1 ITLB 4M page : 4 entries, fully associative
L1 DTLB 4K page : 32 entries, fully associative
L1 DTLB 2M page : 8 entries, fully associative
L1 DTLB 4M page : 4 entries, fully associative
L2 DTLB 4K page : 512 entries, 4-way set associative
L2 ITLB 4K page : 512 entries, 4-way set associative
L1 instr. cache : 64KB, 2-way set associative, 64 byte line siz
L1 data cache : 64KB, 2-way set associative, 64 byte line siz
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 512KB, 16-way set associative, 64 byte line s
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
Addressing capability
---------------------
Physical address bits : 40
Virtual address bits : 48
Example
-------
Optimal block size : 16KB
Will flush Denormals to Zero
Will use SSE2 code
CPU Brand String : AMD Athlon(tm) 64 Processor 2800+
CPU frequency : ~1980 MHz
CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : yes
3DNow! Instructions : yes
3DNow!+ Instructions : yes
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : no
Denormals Are Zeros : yes
Hyper-Threading : no
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : no
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no
CPU cache & TLB info
--------------------
L1 ITLB 4K page : 32 entries, fully associative
L1 ITLB 2M page : 8 entries, fully associative
L1 ITLB 4M page : 4 entries, fully associative
L1 DTLB 4K page : 32 entries, fully associative
L1 DTLB 2M page : 8 entries, fully associative
L1 DTLB 4M page : 4 entries, fully associative
L2 DTLB 4K page : 512 entries, 4-way set associative
L2 ITLB 4K page : 512 entries, 4-way set associative
L1 instr. cache : 64KB, 2-way set associative, 64 byte line siz
L1 data cache : 64KB, 2-way set associative, 64 byte line siz
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 512KB, 16-way set associative, 64 byte line s
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
Addressing capability
---------------------
Physical address bits : 40
Virtual address bits : 48
Example
-------
Optimal block size : 16KB
Will flush Denormals to Zero
Will use SSE2 code
- Učlanjen(a)
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@drfedja:
Koju od 3 verzije pinfo.exe si probao? Nadam se poslednju. Hajde ako ti nije tesko poteraj i onaj 4ji.exe pa postuj rezultat da vidim sta je problem.
Koju od 3 verzije pinfo.exe si probao? Nadam se poslednju. Hajde ako ti nije tesko poteraj i onaj 4ji.exe pa postuj rezultat da vidim sta je problem.
Y
Yoti
Guest
Microsoft Windows XP [Version 5.1.2600]
(C) Copyright 1985-2001 Microsoft Corp.
C:\Documents and Settings\Administrator>C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\Rar$D
R01.546\pinfo.exe
CPU Brand String : Genuine Intel(R) CPU @ 1.86GHz
CPU frequency : ~2690 MHz
CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : no
3DNow! Instructions : no
3DNow!+ Instructions : no
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : yes
SSE4 Instructions : yes
Denormals Are Zeros : yes
Hyper-Threading : no
Dual-Core : yes
Context ID : no
MONITOR/MWAIT : yes
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : yes
SYSCALL/SYSRET : no
CMPXCHG16B : yes
Vanderpool (VMX) : yes
Pacifica (SVM) : no
CPU cache & TLB info
--------------------
L1 ITLB 4K page : 128 entries, 4-way set associative
L1 data cache : 32KB, 8-way set associative, 64 byte line size
Self initializing cache level : yes
Number of threads sharing this cache : 1
Number of processor cores on this die : 2
Physical line partitions : 1
Number of Sets : 64
L2 cache : 2048KB, 8-way set associative, 64 byte line size
Self initializing cache level : yes
Number of threads sharing this cache : 2
Number of processor cores on this die : 2
Physical line partitions : 1
Number of Sets : 4096
Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 48
Example
-------
Optimal block size : 128KB
Will flush Denormals to Zero
Will use SSE4 code
(C) Copyright 1985-2001 Microsoft Corp.
C:\Documents and Settings\Administrator>C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\Rar$D
R01.546\pinfo.exe
CPU Brand String : Genuine Intel(R) CPU @ 1.86GHz
CPU frequency : ~2690 MHz
CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : no
3DNow! Instructions : no
3DNow!+ Instructions : no
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : yes
SSE4 Instructions : yes
Denormals Are Zeros : yes
Hyper-Threading : no
Dual-Core : yes
Context ID : no
MONITOR/MWAIT : yes
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : yes
SYSCALL/SYSRET : no
CMPXCHG16B : yes
Vanderpool (VMX) : yes
Pacifica (SVM) : no
CPU cache & TLB info
--------------------
L1 ITLB 4K page : 128 entries, 4-way set associative
L1 data cache : 32KB, 8-way set associative, 64 byte line size
Self initializing cache level : yes
Number of threads sharing this cache : 1
Number of processor cores on this die : 2
Physical line partitions : 1
Number of Sets : 64
L2 cache : 2048KB, 8-way set associative, 64 byte line size
Self initializing cache level : yes
Number of threads sharing this cache : 2
Number of processor cores on this die : 2
Physical line partitions : 1
Number of Sets : 4096
Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 48
Example
-------
Optimal block size : 128KB
Will flush Denormals to Zero
Will use SSE4 code
fixer
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CPU Brand String : Intel(R) Pentium(R) 4 CPU 2.00GHz
CPU frequency : ~1994 MHz
CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : no
3DNow! Instructions : no
3DNow!+ Instructions : no
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : no
Denormals Are Zeros : yes
Hyper-Threading : no
Dual-Core : no
Context ID : yes
MONITOR/MWAIT : no
x86-64 Instructions : no
No Execute : no
LAHF/SAHF in x86-64 : no
SYSCALL/SYSRET : no
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no
CPU cache & TLB info
--------------------
L1 ITLB 4K page : 128 entries, fully associative
L1 ITLB 2M page : 128 entries, fully associative
L1 ITLB 4M page : 128 entries, fully associative
Unified DTLB 4K : 64 entries, fully associative
Unified DTLB 4M : 64 entries, fully associative
L1 trace cache : 12K uops, 8-way set associative
L1 data cache : 8KB, 4-way set associative, sectored, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 512KB, 8-way set associative, sectored, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 32
Example
-------
Optimal block size : 32KB
Will flush Denormals to Zero
Will use SSE2 code
CPU frequency : ~1994 MHz
CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : no
3DNow! Instructions : no
3DNow!+ Instructions : no
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : no
Denormals Are Zeros : yes
Hyper-Threading : no
Dual-Core : no
Context ID : yes
MONITOR/MWAIT : no
x86-64 Instructions : no
No Execute : no
LAHF/SAHF in x86-64 : no
SYSCALL/SYSRET : no
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no
CPU cache & TLB info
--------------------
L1 ITLB 4K page : 128 entries, fully associative
L1 ITLB 2M page : 128 entries, fully associative
L1 ITLB 4M page : 128 entries, fully associative
Unified DTLB 4K : 64 entries, fully associative
Unified DTLB 4M : 64 entries, fully associative
L1 trace cache : 12K uops, 8-way set associative
L1 data cache : 8KB, 4-way set associative, sectored, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 512KB, 8-way set associative, sectored, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 32
Example
-------
Optimal block size : 32KB
Will flush Denormals to Zero
Will use SSE2 code
M!ST!CX
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CPU Brand String : Intel(R) Pentium(R) D CPU 2.66GHz
CPU frequency : ~3600 MHz
CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : no
3DNow! Instructions : no
3DNow!+ Instructions : no
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : yes
Denormals Are Zeros : yes
Hyper-Threading : no
Dual-Core : yes
Context ID : yes
MONITOR/MWAIT : yes
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : yes
SYSCALL/SYSRET : no
CMPXCHG16B : yes
Vanderpool (VMX) : no
Pacifica (SVM) : no
CPU cache & TLB info
--------------------
L1 ITLB 4K page : 128 entries, fully associative
L1 ITLB 2M page : 128 entries, fully associative
L1 ITLB 4M page : 128 entries, fully associative
Unified DTLB 4K : 64 entries, fully associative
Unified DTLB 4M : 64 entries, fully associative
L1 trace cache : 12K uops, 8-way set associative
L1 data cache : 16KB, 8-way set associative, sectored, 64 byte line size
Self initializing cache level : yes
Number of threads sharing this cache : 1
Number of processor cores on this die : 2
Physical line partitions : 1
Number of Sets : 32
L2 cache : 1024KB, 8-way set associative, sectored, 64 byte line size
Self initializing cache level : yes
Number of threads sharing this cache : 1
Number of processor cores on this die : 2
Physical line partitions : 2
Number of Sets : 1024
Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 48
Example
-------
Optimal block size : 64KB
Will flush Denormals to Zero
Will use SSE3 code
CPU frequency : ~3600 MHz
CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : no
3DNow! Instructions : no
3DNow!+ Instructions : no
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : yes
Denormals Are Zeros : yes
Hyper-Threading : no
Dual-Core : yes
Context ID : yes
MONITOR/MWAIT : yes
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : yes
SYSCALL/SYSRET : no
CMPXCHG16B : yes
Vanderpool (VMX) : no
Pacifica (SVM) : no
CPU cache & TLB info
--------------------
L1 ITLB 4K page : 128 entries, fully associative
L1 ITLB 2M page : 128 entries, fully associative
L1 ITLB 4M page : 128 entries, fully associative
Unified DTLB 4K : 64 entries, fully associative
Unified DTLB 4M : 64 entries, fully associative
L1 trace cache : 12K uops, 8-way set associative
L1 data cache : 16KB, 8-way set associative, sectored, 64 byte line size
Self initializing cache level : yes
Number of threads sharing this cache : 1
Number of processor cores on this die : 2
Physical line partitions : 1
Number of Sets : 32
L2 cache : 1024KB, 8-way set associative, sectored, 64 byte line size
Self initializing cache level : yes
Number of threads sharing this cache : 1
Number of processor cores on this die : 2
Physical line partitions : 2
Number of Sets : 1024
Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 48
Example
-------
Optimal block size : 64KB
Will flush Denormals to Zero
Will use SSE3 code
