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audiofreak

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21.07.2003
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Napisao sam neki rudimentarni programcic koji detektuje mogucnosti procesora. E sad, posto sam ja Intelovac, detekcija najtacnije radi na Intel procesorima :)
Molio bih vlasnike AMD dual-core procesora da poteraju programcic iz attachmenta i da okace ono sto doticni ispise. U pitanju je konzolna aplikacija za sada.
Zanima me da li je detekcija za dual-core ispravna i za AMD (za Intel radi barem kod mene).
Takodje, ako neko ima Pentium EE 955 i to bih voleo da vidim.
 

Prilozi

  • pinfo.zip
    20.1 KB · Pregleda: 105
Evo ja cu okaciti moje, doduse nemam AMD ni 955 vec 630 (racuna se :D).

Kod:
C:\>pinfo
CPU Brand String     : Intel(R) Pentium(R) 4 CPU 3.00GHz
CPU frequency        : ~3014 MHz

CPU Features
------------
Time Stamp Counter   : yes
MMX Instructions     : yes
MMX+ Instructions    : no
3DNow! Instructions  : no
3DNow!+ Instructions : no
SSE Instructions     : yes
SSE2 Instructions    : yes
SSE3 Instructions    : yes
Denormals Are Zeros  : yes
Hyper-Threading      : yes
Dual-Core            : no
Context ID           : yes
MONITOR/MWAIT        : yes
x86-64 Instructions  : yes
No Execute           : yes
LAHF/SAHF in x86-64  : no
SYSCALL/SYSRET       : no
CMPXCHG16B           : yes
Vanderpool (VMX)     : no
Pacifica (SVM)       : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 64 entries, fully associative
L1 ITLB 2M page : 64 entries, fully associative
L1 ITLB 4M page : 64 entries, fully associative
Unified DTLB 4K : 64 entries, fully associative
Unified DTLB 4M : 64 entries, fully associative
L1 trace cache  : 12K uops, 8-way set associative
L1 data cache   : 16KB, 8-way set associative, sectored, 64 byte line size
Self initializing cache level         : yes
Number of threads sharing this cache  : 2
Number of processor cores on this die : 1
Physical line partitions              : 1
Number of Sets                        : 32
L2 cache        : 2048KB, 8-way set associative, 64 byte line size
Self initializing cache level         : yes
Number of threads sharing this cache  : 2
Number of processor cores on this die : 1
Physical line partitions              : 2
Number of Sets                        : 2048

Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 48

Example
-------
Optimal block size : 128KB
Will use Hyper-Threaded code
Will flush Denormals to Zero
Will use SSE3 code
 
Hvala :D
Zaboravih da okacim kako to izgleda kod mene...
Kod:
CPU Brand String     : Intel(R) Pentium(R) D CPU 3.00GHz
CPU frequency        : ~3010 MHz

CPU Features
------------
Time Stamp Counter   : yes
MMX Instructions     : yes
MMX+ Instructions    : no
3DNow! Instructions  : no
3DNow!+ Instructions : no
SSE Instructions     : yes
SSE2 Instructions    : yes
SSE3 Instructions    : yes
Denormals Are Zeros  : yes
Hyper-Threading      : no
Dual-Core            : yes
Context ID           : yes
MONITOR/MWAIT        : yes
x86-64 Instructions  : yes
No Execute           : no
LAHF/SAHF in x86-64  : yes
SYSCALL/SYSRET       : no
CMPXCHG16B           : yes
Vanderpool (VMX)     : yes
Pacifica (SVM)       : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 128 entries, fully associative
L1 ITLB 2M page : 128 entries, fully associative
L1 ITLB 4M page : 128 entries, fully associative
Unified DTLB 4K : 64 entries, fully associative
Unified DTLB 4M : 64 entries, fully associative
L1 trace cache  : 12K uops, 8-way set associative
L1 data cache   : 16KB, 8-way set associative, sectored, 64 byte line size
Self initializing cache level         : yes
Number of threads sharing this cache  : 1
Number of processor cores on this die : 2
Physical line partitions              : 1
Number of Sets                        : 32
L2 cache        : 2048KB, 8-way set associative, 64 byte line size
Self initializing cache level         : yes
Number of threads sharing this cache  : 1
Number of processor cores on this die : 2
Physical line partitions              : 2
Number of Sets                        : 2048

Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 48

Example
-------
Optimal block size : 128KB
Will flush Denormals to Zero
Will use SSE3 code

EDIT:
Uploadovana nova verzija, ispravljeno potencijalno deljenje nulom :D
 

Prilozi

  • pinfo.zip
    20.1 KB · Pregleda: 84
Poslednja izmena:
mis'im, šta reći:
----------------------------------------------

CPU frequency : ~0 MHz
CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : no
3DNow! Instructions : no
3DNow!+ Instructions : no
SSE Instructions : yes
SSE2 Instructions : no
SSE3 Instructions : no
Denormals Are Zeros : no
Hyper-Threading : no
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : no
No Execute : no
LAHF/SAHF in x86-64 : no
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
-- More --
Pacifica (SVM) : no
CPU cache & TLB info
--------------------
L1 ITLB 4K page : 32 entries, 4-way set associative
L1 ITLB 4M page : 2 entries, fully associative
Unified DTLB 4K : 64 entries, 4-way set associative
Unified DTLB 4M : 8 entries, 4-way set associative
L1 instr. cache : 16KB, 4-way set associative, 32 byte line size
L1 data cache : 16KB, 4-way set associative, 32 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 256KB, 8-way set associative, 32 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
Addressing capability
-- More --
---------------------
Physical address bits : 36
Virtual address bits : 32
Example
-------
Optimal block size : 16KB
Will use SSE code
 
Intel Penti(J)um D 650

Kod:
CPU Brand String     : Intel(R) Pentium(R) 4 CPU 3.40GHz
CPU frequency        : ~3391 MHz

CPU Features
------------
Time Stamp Counter   : yes
MMX Instructions     : yes
MMX+ Instructions    : no
3DNow! Instructions  : no
3DNow!+ Instructions : no
SSE Instructions     : yes
SSE2 Instructions    : yes
SSE3 Instructions    : yes
Denormals Are Zeros  : yes
Hyper-Threading      : yes
Dual-Core            : no
Context ID           : yes
MONITOR/MWAIT        : yes
x86-64 Instructions  : yes
No Execute           : no
LAHF/SAHF in x86-64  : no
SYSCALL/SYSRET       : no
CMPXCHG16B           : yes
Vanderpool (VMX)     : no
Pacifica (SVM)       : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 64 entries, fully associative
L1 ITLB 2M page : 64 entries, fully associative
L1 ITLB 4M page : 64 entries, fully associative
Unified DTLB 4K : 64 entries, fully associative
Unified DTLB 4M : 64 entries, fully associative
L1 trace cache  : 12K uops, 8-way set associative
L1 data cache   : 16KB, 8-way set associative, sectored, 64 byte line size
Self initializing cache level         : yes
Number of threads sharing this cache  : 2
Number of processor cores on this die : 1
Physical line partitions              : 1
Number of Sets                        : 32
L2 cache        : 2048KB, 8-way set associative, 64 byte line size
Self initializing cache level         : yes
Number of threads sharing this cache  : 2
Number of processor cores on this die : 1
Physical line partitions              : 2
Number of Sets                        : 2048

Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 48

Example
-------
Optimal block size : 128KB
Will use Hyper-Threaded code
Will flush Denormals to Zero
Will use SSE3 code
 
zokish je napisao(la):
mis'im, šta reći:
----------------------------------------------

CPU frequency : ~0 MHz

Koji OS koristis? Koji procesor? Ne merim ja frekvenciju nego citam iz registry-ja -- HARDWARE\DESCRIPTION\System\CentralProcessor\0 i naravno ne proveravam da li je smislena vrednost jer me mrzi
:smoke:
 
Poslednja izmena:
Evo radi i sa Pentium M :)


Kod:
CPU Brand String: Intel(R) Pentium(R) M processor 1.73GHz  
CPU frequency: ~1733 MHz    

CPU Features  
------------  
Time Stamp Counter: yes  
MMX Instructions: yes  
MMX+ Instructions: no  
3DNow! Instructions: no  
3DNow!+ Instructions: no  
SSE Instructions: yes  
SSE2 Instructions: yes  
SSE3 Instructions: no  
Denormals Are Zeros: yes  
Hyper-Threading: no  
Dual-Core: no  
Context ID: no  
MONITOR/MWAIT: no  
x86-64 Instructions: no  
No Execute: no  
LAHF/SAHF in x86-64: no  
SYSCALL/SYSRET: no  
CMPXCHG16B: no  
Vanderpool (VMX): no  
Pacifica (SVM): no    

CPU cache & TLB info  
-------------------- 
L1 ITLB 4K page : 128 entries, 4-way set associative  
L1 ITLB 4M page : 2 entries, fully associative  
Unified DTLB 4K : 128 entries, 4-way set associative  
Unified DTLB 4M : 8 entries, 4-way set associative  
L1 data cache   : 32KB, 8-way set associative, 64 byte line size 
 Self initializing cache level: no  
Number of threads sharing this cache: 0  
Number of processor cores on this die: 0  
Physical line partitions: 0  
Number of Sets: 0  
L2 cache: 2048KB, 8-way set associative, 64 byte line size  
Self initializing cache level :no  
Number of threads sharing this cache: 0  
Number of processor cores on this die: 0  
Physical line partitions: 0  
Number of Sets: 0    
Addressing capability 
 ---------------------  
Physical address bits : 32  
Virtual address bits : 32    
Example  
-------  
Optimal block size : 128KB  
Will flush Denormals to Zero  
Will use SSE2 code
 
Poslednja izmena:
Evo i AthlonXP
 

Prilozi

  • untitled.JPG
    untitled.JPG
    84.2 KB · Pregleda: 101
Kod mene prog puca :S: Ono "has encoutered an error, and needs to close..."
 
Dorry je napisao(la):
Kod mene prog puca :S: Ono "has encoutered an error, and needs to close..."

1. Jesi probao i drugi attachment koji sam okacio? Prvi je imao potencijalni bug (deljenje nulom ukoliko cpu ne vrati smislen broj).
2. Jel puca pre nego sto bilo sta ispise ili negde u sred?
3. Ako mozes da mi kazes adresu na kojoj puca pa da pogledam (kikni na details kad pukne)?
 
Poslednja izmena:
Ajde vi sa dual Opteronima i x2 gde ste? :trust: Da sam napisao "amd je sr.nje" svi bi se vec javili da nesto kazu :d
 
Poslednja izmena:
Microsoft Windows XP [Version 5.1.2600]
(C) Copyright 1985-2001 Microsoft Corp.

C:\Documents and Settings\My Documents\pinf
o.exe"
CPU Brand String : Intel(R) Pentium(R) 4 CPU 3.40GHz
CPU frequency : ~3400 MHz

CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : no
3DNow! Instructions : no
3DNow!+ Instructions : no
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : yes
Denormals Are Zeros : yes
Hyper-Threading : yes
Dual-Core : no
Context ID : yes
MONITOR/MWAIT : yes
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : no
SYSCALL/SYSRET : no
CMPXCHG16B : yes
Vanderpool (VMX) : no
Pacifica (SVM) : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 64 entries, fully associative
L1 ITLB 2M page : 64 entries, fully associative
L1 ITLB 4M page : 64 entries, fully associative
Unified DTLB 4K : 64 entries, fully associative
Unified DTLB 4M : 64 entries, fully associative
L1 trace cache : 12K uops, 8-way set associative
L1 data cache : 16KB, 8-way set associative, sectored, 64 byte line size
Self initializing cache level : yes
Number of threads sharing this cache : 2
Number of processor cores on this die : 1
Physical line partitions : 1
Number of Sets : 32
L2 cache : 2048KB, 8-way set associative, 64 byte line size
Self initializing cache level : yes
Number of threads sharing this cache : 2
Number of processor cores on this die : 1
Physical line partitions : 2
Number of Sets : 2048

Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 48

Example
-------
Optimal block size : 128KB
Will use Hyper-Threaded code
Will flush Denormals to Zero
Will use SSE3 code
 
Evo i moj praistorijski :d pentijum 2 350@466 MHz:


C:\Documents and Settings\Administrator>"C:\Documents and Settings\Administrator
\Desktop\pinfo\pinfo.exe"
CPU frequency : ~467 MHz

CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : no
3DNow! Instructions : no
3DNow!+ Instructions : no
SSE Instructions : no
SSE2 Instructions : no
SSE3 Instructions : no
Denormals Are Zeros : no
Hyper-Threading : no
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : no
No Execute : yes
LAHF/SAHF in x86-64 : yes
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 32 entries, 4-way set associative
L1 ITLB 4M page : 2 entries, fully associative
Unified DTLB 4K : 64 entries, 4-way set associative
Unified DTLB 4M : 8 entries, 4-way set associative
L1 instr. cache : 16KB, 4-way set associative, 32 byte line size
L1 data cache : 16KB, 4-way set associative, 32 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 512KB, 4-way set associative, 32 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0

Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 32

Example
-------
Optimal block size : 64KB
Will use MMX code

C:\Documents and Settings\Administrator>
 
... samo mi se za jedan veoma kratak trenutak pojavi tamni prozor "command prompta"
Intel PENTIUM D920, MB INTEL 945 GNTL, 2*512 DDRII 667 Geil
 
Poslednja izmena:
@audiofreak: Probao sam i jedan i drugi attach, sada vise ne izbacuje error, nego isto kao i kod markoncic-a - na tren izbaci CMD prompt prozor i ugasi ga :(
 
@audiofreak
amd populacija ignorise tvoj program iako sasvim lepo radi, ali ako cita registry onda je pitanje da li win lepo radi.

CPU Brand String : AMD Sempron(tm) Processor 2800+
CPU frequency : ~2485 MHz

CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : yes
3DNow! Instructions : yes
3DNow!+ Instructions : yes
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : yes
Denormals Are Zeros : yes
Hyper-Threading : no
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : yes
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 32 entries, fully associative
L1 ITLB 2M page : 8 entries, fully associative
L1 ITLB 4M page : 4 entries, fully associative
L1 DTLB 4K page : 32 entries, fully associative
L1 DTLB 2M page : 8 entries, fully associative
L1 DTLB 4M page : 4 entries, fully associative
L2 DTLB 4K page : 512 entries, 4-way set associative
L2 ITLB 4K page : 512 entries, 4-way set associative
L1 instr. cache : 64KB, 2-way set associative, 64 byte line size
L1 data cache : 64KB, 2-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 256KB, 16-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0

Addressing capability
---------------------
Physical address bits : 40
Virtual address bits : 48

Example
-------
Optimal block size : 8KB
Will flush Denormals to Zero
Will use SSE3 code
 
Evo radi i sa socket 754 Athlon-om
Kod:
C:\pinfo>pinfo.exe
CPU Brand String     : AMD Athlon(tm) 64 Processor 2800+
CPU frequency        : ~2303 MHz

CPU Features
------------
Time Stamp Counter   : yes
MMX Instructions     : yes
MMX+ Instructions    : yes
3DNow! Instructions  : yes
3DNow!+ Instructions : yes
SSE Instructions     : yes
SSE2 Instructions    : yes
SSE3 Instructions    : no
Denormals Are Zeros  : yes
Hyper-Threading      : no
Dual-Core            : no
Context ID           : no
MONITOR/MWAIT        : no
x86-64 Instructions  : yes
No Execute           : yes
LAHF/SAHF in x86-64  : no
SYSCALL/SYSRET       : yes
CMPXCHG16B           : no
Vanderpool (VMX)     : no
Pacifica (SVM)       : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 32 entries, fully associative
L1 ITLB 2M page : 8 entries, fully associative
L1 ITLB 4M page : 4 entries, fully associative
L1 DTLB 4K page : 32 entries, fully associative
L1 DTLB 2M page : 8 entries, fully associative
L1 DTLB 4M page : 4 entries, fully associative
L2 DTLB 4K page : 512 entries, 4-way set associative
L2 ITLB 4K page : 512 entries, 4-way set associative
L1 instr. cache : 64KB, 2-way set associative, 64 byte line size
L1 data cache   : 64KB, 2-way set associative, 64 byte line size
Self initializing cache level         : no
Number of threads sharing this cache  : 0
Number of processor cores on this die : 0
Physical line partitions              : 0
Number of Sets                        : 0
L2 cache        : 512KB, 16-way set associative, 64 byte line size
Self initializing cache level         : no
Number of threads sharing this cache  : 0
Number of processor cores on this die : 0
Physical line partitions              : 0
Number of Sets                        : 0

Addressing capability
---------------------
Physical address bits : 40
Virtual address bits : 48

Example
-------
Optimal block size : 16KB
Will flush Denormals to Zero
Will use SSE2 code

C:\pinfo>cd pinfo
 
D:\Documents and Settings\Vlada\Desktop\pinfo>pinfo.exe
CPU Brand String : Intel(R) Pentium(R) D CPU 2.80GHz
CPU frequency : ~2799 MHz

CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : no
3DNow! Instructions : no
3DNow!+ Instructions : no
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : yes
Denormals Are Zeros : yes
Hyper-Threading : no
Dual-Core : yes
Context ID : yes
MONITOR/MWAIT : yes
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : yes
SYSCALL/SYSRET : no
CMPXCHG16B : yes
Vanderpool (VMX) : yes
Pacifica (SVM) : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 128 entries, fully associative
L1 ITLB 2M page : 128 entries, fully associative
L1 ITLB 4M page : 128 entries, fully associative
Unified DTLB 4K : 64 entries, fully associative
Unified DTLB 4M : 64 entries, fully associative
L1 trace cache : 12K uops, 8-way set associative
L1 data cache : 16KB, 8-way set associative, sectored, 64 byte line size
Self initializing cache level : yes
Number of threads sharing this cache : 1
Number of processor cores on this die : 2
Physical line partitions : 1
Number of Sets : 32
L2 cache : 2048KB, 8-way set associative, 64 byte line size
Self initializing cache level : yes
Number of threads sharing this cache : 1
Number of processor cores on this die : 2
Physical line partitions : 2
Number of Sets : 2048

Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 48

Example
-------
Optimal block size : 128KB
Will flush Denormals to Zero
Will use SSE3 code

D:\Documents and Settings\Vlada\Desktop\pinfo>
 
CPU Brand String : AMD Athlon(tm) 64 Processor 3500+
CPU frequency : ~2210 MHz

CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : yes
3DNow! Instructions : yes
3DNow!+ Instructions : yes
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : no
Denormals Are Zeros : yes
Hyper-Threading : no
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : no
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 32 entries, fully associative
L1 ITLB 2M page : 8 entries, fully associative
L1 ITLB 4M page : 4 entries, fully associative
L1 DTLB 4K page : 32 entries, fully associative
L1 DTLB 2M page : 8 entries, fully associative
L1 DTLB 4M page : 4 entries, fully associative
L2 DTLB 4K page : 512 entries, 4-way set associative
L2 ITLB 4K page : 512 entries, 4-way set associative
L1 instr. cache : 64KB, 2-way set associative, 64 byte line size
L1 data cache : 64KB, 2-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 512KB, 16-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0

Addressing capability
---------------------
Physical address bits : 40
Virtual address bits : 48

Example
-------
Optimal block size : 16KB
Will flush Denormals to Zero
Will use SSE2 code
 
Da sam napisao "amd je sr.nje" svi bi se vec javili da nesto kazu

Pa ne možeš napisati da je ******,jer to nije.Ali ti to ionako znaš ;)

Uspio sam ga pokrenuti iz Command Prompt-a.

CPU Brand String : AMD Athlon(tm) 64 Processor 3200+
CPU frequency : ~2500 MHz

CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : yes
3DNow! Instructions : yes
3DNow!+ Instructions : yes
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : yes
Denormals Are Zeros : yes
Hyper-Threading : no
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : yes
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 32 entries, fully associative
L1 ITLB 2M page : 8 entries, fully associative
L1 ITLB 4M page : 4 entries, fully associative
L1 DTLB 4K page : 32 entries, fully associative
L1 DTLB 2M page : 8 entries, fully associative
L1 DTLB 4M page : 4 entries, fully associative
L2 DTLB 4K page : 512 entries, 4-way set associative
L2 ITLB 4K page : 512 entries, 4-way set associative
L1 instr. cache : 64KB, 2-way set associative, 64 byte line size
L1 data cache : 64KB, 2-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 512KB, 16-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0

Addressing capability
---------------------
Physical address bits : 40
Virtual address bits : 48

Example
-------
Optimal block size : 16KB
Will flush Denormals to Zero
Will use SSE3 code
 
Poslednja izmena:
CPU Brand String : AMD Athlon(tm) XP 2200+
CPU frequency : ~1804 MHz

CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : yes
3DNow! Instructions : yes
3DNow!+ Instructions : yes
SSE Instructions : yes
SSE2 Instructions : no
SSE3 Instructions : no
Denormals Are Zeros : no
Hyper-Threading : no
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : no
No Execute : no
LAHF/SAHF in x86-64 : no
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 16 entries, fully associative
L1 ITLB 2M page : 8 entries, fully associative
L1 ITLB 4M page : 4 entries, fully associative
L1 DTLB 4K page : 32 entries, fully associative
L1 DTLB 2M page : 8 entries, 4-way set associative
L1 DTLB 4M page : 4 entries, 4-way set associative
L2 DTLB 4K page : 256 entries, 4-way set associative
L2 ITLB 4K page : 256 entries, 4-way set associative
L1 instr. cache : 64KB, 2-way set associative, 64 byte line size
L1 data cache : 64KB, 2-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 256KB, 16-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0

Addressing capability
---------------------
Physical address bits : 34
Virtual address bits : 32

Example
-------
Optimal block size : 8KB
Will use SSE code
 
R_U_S je napisao(la):
Kod:
No Execute : yes
LAHF/SAHF in x86-64 : yes
SYSCALL/SYSRET : yes

Hvala, ovo ukazuje na gresku u detekciji, bice ispravljeno.

Dorry je napisao(la):
@audiofreak: Probao sam i jedan i drugi attach, sada vise ne izbacuje error, nego isto kao i kod markoncic-a - na tren izbaci CMD prompt prozor i ugasi ga :(

markoncic je napisao(la):
... samo mi se za jedan veoma kratak trenutak pojavi tamni prozor "command prompta"

Uputstvo:

1. Raspakuj pinfo.zip na c:\
2. Klikni na Start->Programs->Accessories->Command Prompt
3. Otkucaj c: i pritisni Enter
4. Otkucaj cd \ i ponovo Enter
5. Otkucaj pinfo.exe i ponovo Enter

Tekst koji izadje ubaci ovde.

Umesto 5 moze i ovako:

5. pinfo.exe >report.txt

Onda je lakse prebaciti izvestaj iz tekst fajla nego raditi copy & paste iz prozora.

Ako vam je suvise komplikovano nemojte se muciti.

otogrunt je napisao(la):
ali ako cita registry onda je pitanje da li win lepo radi.

Cita samo radnu frekvenciju iz registrija, a to je uglavnom tacno. Ostalo se detektuje.

Znaci ni jedno A64 jezgro pre Venice (SSE3) nema LAHF/SAHF instrukcije u 64-bitnom modu?!? A toliko su pljuvali Intel sto je to izostavio u svojim prvim revizijama EM64T... c, c, c...

Ne bilo vam tesko napisite i socket kad probate. U prilogu verzija sa sitnim ispravkama (za R_U_S-a i njegov 64-bitni Pentiun II :D). Svi koji testiraju prvi put neka koriste novu verziju, ko je vec testirao ne mora ponovo osim ako mu nije dosadno. :D
 

Prilozi

  • pinfo.zip
    20.1 KB · Pregleda: 31
Poslednja izmena:
audiofreak je napisao(la):
Ajde vi sa dual Opteronima i x2 gde ste? :trust: Da sam napisao "amd je sr.nje" svi bi se vec javili da nesto kazu :d

renderujemo, pa ne stizemo ,)


CPU Brand String : Dual Core AMD Opteron(tm) Processor 170
CPU frequency : ~2713 MHz

CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : yes
3DNow! Instructions : yes
3DNow!+ Instructions : yes
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : yes
Denormals Are Zeros : yes
Hyper-Threading : yes
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : yes
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 32 entries, fully associative
L1 ITLB 2M page : 8 entries, fully associative
L1 ITLB 4M page : 4 entries, fully associative
L1 DTLB 4K page : 32 entries, fully associative
L1 DTLB 2M page : 8 entries, fully associative
L1 DTLB 4M page : 4 entries, fully associative
L2 DTLB 4K page : 512 entries, 4-way set associative
L2 ITLB 4K page : 512 entries, 4-way set associative
L1 instr. cache : 64KB, 2-way set associative, 64 byte line size
L1 data cache : 64KB, 2-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 1024KB, 16-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0

Addressing capability
---------------------
Physical address bits : 40
Virtual address bits : 48

Example
-------
Optimal block size : 32KB
Will use Hyper-Threaded code
Will flush Denormals to Zero
Will use SSE3 code


CPU Brand String : AMD Athlon(tm) 64 X2 Dual Core Processor 4400+
CPU frequency : ~2596 MHz

CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : yes
3DNow! Instructions : yes
3DNow!+ Instructions : yes
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : yes
Denormals Are Zeros : yes
Hyper-Threading : yes
Dual-Core : no
Context ID : no
MONITOR/MWAIT : no
x86-64 Instructions : yes
No Execute : yes
LAHF/SAHF in x86-64 : yes
SYSCALL/SYSRET : yes
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 32 entries, fully associative
L1 ITLB 2M page : 8 entries, fully associative
L1 ITLB 4M page : 4 entries, fully associative
L1 DTLB 4K page : 32 entries, fully associative
L1 DTLB 2M page : 8 entries, fully associative
L1 DTLB 4M page : 4 entries, fully associative
L2 DTLB 4K page : 512 entries, 4-way set associative
L2 ITLB 4K page : 512 entries, 4-way set associative
L1 instr. cache : 64KB, 2-way set associative, 64 byte line size
L1 data cache : 64KB, 2-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 1024KB, 16-way set associative, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0

Addressing capability
---------------------
Physical address bits : 40
Virtual address bits : 48

Example
-------
Optimal block size : 32KB
Will use Hyper-Threaded code
Will flush Denormals to Zero
Will use SSE3 code

program iz poslednjeg atachmenta
 
Radi, evo sta kaze :) :

Microsoft Windows XP [Version 5.1.2600]
(C) Copyright 1985-2001 Microsoft Corp.

C:\Documents and Settings\Dorian>pinfo.exe
CPU Brand String : Intel(R) Pentium(R) 4 CPU 2.80GHz
CPU frequency : ~2806 MHz

CPU Features
------------
Time Stamp Counter : yes
MMX Instructions : yes
MMX+ Instructions : no
3DNow! Instructions : no
3DNow!+ Instructions : no
SSE Instructions : yes
SSE2 Instructions : yes
SSE3 Instructions : no
Denormals Are Zeros : yes
Hyper-Threading : yes
Dual-Core : no
Context ID : yes
MONITOR/MWAIT : no
x86-64 Instructions : no
No Execute : no
LAHF/SAHF in x86-64 : no
SYSCALL/SYSRET : no
CMPXCHG16B : no
Vanderpool (VMX) : no
Pacifica (SVM) : no

CPU cache & TLB info
--------------------
L1 ITLB 4K page : 64 entries, fully associative
L1 ITLB 2M page : 64 entries, fully associative
L1 ITLB 4M page : 64 entries, fully associative
Unified DTLB 4K : 64 entries, fully associative
Unified DTLB 4M : 64 entries, fully associative
L1 trace cache : 12K uops, 8-way set associative
L1 data cache : 8KB, 4-way set associative, sectored, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0
L2 cache : 512KB, 8-way set associative, sectored, 64 byte line size
Self initializing cache level : no
Number of threads sharing this cache : 0
Number of processor cores on this die : 0
Physical line partitions : 0
Number of Sets : 0

Addressing capability
---------------------
Physical address bits : 36
Virtual address bits : 32

Example
-------
Optimal block size : 32KB
Will use Hyper-Threaded code
Will flush Denormals to Zero
Will use SSE2 code
 
@Ji:
Samo za tebe u attachmentu programcic koji direktno ispisuje vrednosti registara, poteraj to na ta dva procesora ako mozes pa mi okaci ovde.

Vi ostali nemojte startovati program jer nema smisla, trebaju mi podaci samo za dual-core opteron ili x2 posto mi detekcija za njih ne radi kako treba. Taj AMD vazda nesto komplikuje i prijavljuje na 100 nacina na 200 razlicitih mesta :mad:, posle se cude sto optimizacije za Intel ne rade na njihovim procesorima, satro namerno ih neko sabotira. Gotovo sam siguran da je samo zbog toga sto ljude mrzi da pisu kilometarske nested IF blokove. :trust:
 

Prilozi

  • 4ji.zip
    15.5 KB · Pregleda: 29
Poslednja izmena:
Kod:
CPUID fn()      EAX             EBX             ECX             EDX
0x00000001      0x00020F32      0x01020800      0x00000001      0x178BFBFF
0x80000008      0x00003028      0x00000000      0x00000001      0x00000000

isto je i za opteron170 i x2 4400+
 
Vrh Dno