TR: Does the Parhelia chip have any provisions for memory bandwidth conservation? If so, which techniques are implemented—Z compression, occlusion culling, fast Z clear? I see it has a "depth acceleration unit for advanced Z processing," but I'm looking for more detail.
DW: The Depth Acceleration unit and Depth Cache deals with the Z-buffer and managing access to the Z-buffer in an efficient way. This area includes logic to perform fast Z clears and also sophisticated logic to queue up Z-reads and Z-writes so that they are always done in burst access. And more generally, while Parhelia-512 has a great deal of raw memory bandwidth, it is an intelligent memory controller whose architecture allows granular access of data and also optimizes the access from the intensity, depth, fragment and texture buffers through multiple independent sub-controllers.
The overall architecture of the entire chip is extremely complex with various optimization techniques. Some topline optimizations are the inclusion of fast Z clears and multiple large caches to hide page breaks and to maximize burst efficiency. If you look on the chip block diagram you will see that the depth unit, Fragment AA unit, pixel unit, texture units and the display units all interact with the 512-bit Memory controller array. Each of these sub-units has specific logic to optimize memory efficiency, and the memory controller array itself then arbitrates between all of the different requests sent by these different units. There are multiple independent controllers in this array and they can access different information simultaneously.
